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1/19 october 2004 vn920dsp high side driver rev. 2 table 1. general features n cmos compatible input n on state open load detection n off state open load detection n shorted load protection n undervoltage and overvoltage shutdown n protection against loss of ground n very low stand-by current n reverse battery protection (*) description the vn920dsp is a monolithic device made by using stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). figure 1. package active current limitation combined with thermal shutdown and automatic restart protect the device against overload. the device detects open load condition both is on and off state. output shorted to v cc is detected in the off state. device automatically turns off in case of ground pin disconnection. table 2. order codes note: (*) see application schematic at page 9 typ e r ds(on) i out v cc vn920dsp 16 m w 25 a 36 v 1 10 powerso-10 package tube tape and reel powerso-10 ? vn920dsp vn920dsp13tr
vn920dsp 2/19 figure 2. block diagram table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 25 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5k w; c=100pf) - input - current sense - output - v cc 4000 4000 5000 5000 v v v v e max maximum switching energy (l=0.25mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =45a) 362 mj p tot power dissipation t c =25c 96.1 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c undervoltage overtemperature v cc gnd input output overvoltage current limiter logic driver power clamp status v cc clamp on state openload off state openload and output shorted to v cc detection detection detection detection detection
3/19 vn920dsp figure 3. configuration diagram (top view) & suggested connections for unused and n.c. pins figure 4. current and voltage conventions table 4. thermal data note: (1) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m m thick). note: (2) when mounted on a standard single-sided fr-4 board with 6 cm 2 of cu (at least 35 m m thick). symbol parameter value unit r thj-case thermal resistance junction-case max 1.3 c/w r thj-amb thermal resistance junction-ambient max 51.3 (1) 37 (2) c/w 1 2 3 4 5 6 7 8 9 10 11 output output n.c. output output ground input status n.c. n.c. v cc connection / pin status n.c. output input floating x x x x to ground x through 10k w resistor i s i gnd v cc v cc v sense output i out current sense i sense input i in v in v out gnd v f
vn920dsp 4/19 electrical characteristics (8v 5/19 vn920dsp electrical characteristics (continued) table 8. vcc - output diode table 9. status pin table 10. protections (see note 1) note: 1. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic sign als must be used together with a proper software strategy. if the device operates under abnormal conditions this software must limit the du ration and number of activation cycles. table 11. openload detection symbol parameter test conditions min typ max unit v f forward on voltage -i out =5a; t j =150c 0.6 v symbol parameter test conditions min typ max unit v stat status low output voltage i stat =1.6ma 0.5 v i lstat status leakage current normal operation v stat =5v 10 m a c stat status pin input capacitance normal operation v stat =5v 100 pf v scl status clamp voltage i stat =1ma i stat =-1ma 66.8 -0.7 8v v symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload condition t j >t tsd 20 m s i lim current limitation 5.5v vn920dsp 6/19 figure 5. figure 6. switching time waveforms v in v stat t dol(off) open load status timing (with external pull-up) overtemp status timing i out < i ol v out > v ol t dol(on) t j > t tsd v in v stat t sdl t sdl t t v out v in 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on)
7/19 vn920dsp table 12. truth table table 13. electrical transient requirements on v cc pin conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 w iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5c e e e class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
vn920dsp 8/19 figure 7. waveforms open load without external pull-up status input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc v cc >v ov status input status status input status input open load with external pull-up undefined load voltage v cc v ol v ol
9/19 vn920dsp figure 8. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input line is also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input pin is to leave it unconnected, while unused sense pin has to be connected to ground pin. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. m c i/os protection: if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w. v cc gnd output d gnd r gnd d ld m c +5v r prot v gnd status input +5v r prot
vn920dsp 10/19 figure 9. off state output current figure 10. high level input current figure 11. input low level figure 12. input clamp voltage figure 13. input high level figure 14. input hysteresis voltage -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 1 2 3 4 5 6 7 8 9 il(off1) (ua) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v)
11/19 vn920dsp figure 15. overvoltage shutdown figure 16. turn-on voltage slope figure 17. on state resistance vs t case figure 18. i lim vs t case figure 19. turn-off voltage slope figure 20. on state resistance vs v cc -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 250 300 350 400 450 500 550 600 650 700 dvout/dt(on) (v/ms) vcc=13v rl=1.3ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 5 10 15 20 25 30 35 40 45 50 ron (mohm) iout=10a vcc=8v; 36v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 10 20 30 40 50 60 70 80 90 100 ilim (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 50 100 150 200 250 300 350 400 450 500 550 dvout/dt(off) (v/ms) vcc=13v rl=1.3ohm 5 10152025303540 vcc (v) 0 5 10 15 20 25 30 35 40 45 50 ron (mohm) tc= - 40oc tc= 25oc tc= 150oc
vn920dsp 12/19 figure 21. status leakage current figure 22. status clamp voltage figure 23. status low output voltage -50 -25 0 25 50 75 100 125 150 175 tc ( o c) 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 ilstat( m a) vstat=5v -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vscl (v) istat=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 vstat (v) istat=1.6ma
13/19 vn920dsp figure 24. maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. 1 10 100 0.1 1 10 100 l(mh) i lmax (a) a b c v in , i l t demagnetization demagnetization demagnetization
vn920dsp 14/19 powerso-10? thermal data figure 25. powerso-10? pc board figure 26. r thj-amb vs pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: from minimum pad lay-out to 8cm 2 ). 30 35 40 45 50 55 0246810 pcb cu heatsink area (cm^2) rthj_amb (c/w) tj-tamb=50c
15/19 vn920dsp figure 27. powerso-10 thermal impedance junction ambient single pulse figure 28. thermal fitting model of a double channel hsd in powerso-10 pulse calculation formula table 14. thermal parameter 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) footprint 6 cm 2 t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj area/island (cm 2 ) footprint 6 r1 (c/w) 0.02 r2 (c/w) 0.1 r3( c/w) 0.2 r4 (c/w) 0.8 r5 (c/w) 12 r6 (c/w) 37 22 c1 (w.s/c) 0.0015 c2 (w.s/c) 7.00e-03 c3 (w.s/c) 0.015 c4 (w.s/c) 0.3 c5 (w.s/c) 0.75 c6 (w.s/c) 3 5 z th d r th d z thtp 1 d C () + = where d t p t =
vn920dsp 16/19 package mechanical table 15. powerso-10? mechanical data note: (*) muar only poa p013p figure 29. powerso-10? package dimensions symbol millimeters min typ max a 3.35 3.65 a (*) 3.4 3.6 a1 0.00 0.10 b 0.40 0.60 b (*) 0.37 0.53 c 0.35 0.55 c (*) 0.23 0.32 d 9.40 9.60 d1 7.40 7.60 e 9.30 9.50 e2 7.20 7.60 e2 (*) 7.30 7.50 e4 5.90 6.10 e4 (*) 5.90 6.30 e 1.27 f 1.25 1.35 f (*) 1.20 1.40 h 13.80 14.40 h (*) 13.85 14.35 h 0.50 l 1.20 1.80 l (*) 0.80 1.10 a 0o 8o a (*) 2o 8o detail "a" plane seating a l a1 f a1 h a d d1 = = = = e4 0.10 a c a b b detail "a" seating plane e2 10 1 eb he 0.25 p095a
17/19 vn920dsp figure 30. powerso-10 ? suggested pad layout and tube shipment (no suffix) figure 31. tape and reel shipment (suffix 13tr) 6. 30 10.8 - 11 14.6 - 14.9 9.5 1 2 3 4 5 1.27 0.67 - 0.73 0. 54 - 0. 6 10 9 8 7 6 b a c c a b muar casablanca all dimensions are in mm. base q.ty bulk q.ty tube length ( 0.5) a b c ( 0.1) casablanca 50 1000 532 10.4 16.4 0.8 muar 50 1000 532 4.9 17.2 0.8 reel dimensions all dimensions are in mm. base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
vn920dsp 18/19 revision history date revision description of changes sep. 2004 1 - first issue. oct. 2004 2 - minor text change.
19/19 vn920dsp information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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